1. Field of the Invention
The present invention relates to a semiconductor integrated circuit, and in particular to the frequency division of a clock pulse signal.
2. Description of Related Art
Conventionally, clock pulse signals required for circuits need to be supplied in accordance with the respective circuits. However, providing a plurality of clock oscillators for generating such clock pulse signals increases the circuit size. One method for avoiding an increase in the circuit size is to generate the clock pulse signals by dividing the frequency of a high-speed clock pulse signal generated from one clock oscillator. Here, dividing the frequency of a clock pulse signal refers to a repetitive operation of counting pulses of the clock pulse signal with use of a frequency division counter, causing an output signal to rise or fall when the counter value reaches a predetermined setting value, and then resetting the counter value to zero. For example, with the setting value of six, a clock pulse signal is generated by dividing by six the frequency of a high-speed clock pulse signal, provided that rising edges and falling edges are both to be counted. In other words, the generated clock pulse signal remains High (hereinafter, “Hi”) for three clocks and Low for another three clocks.
However, the above-described method only enables an integral frequency division of a high-speed clock pulse signal, and not a fractional frequency division of the high-speed clock pulse signal.
To realize the fractional frequency division, Patent Document 1 (Japanese National Publication of the Translated Version of PCT Application No. 2004-519958) discloses a technique for generating a pulse signal whose cycle approximates a desired cycle by switching the number of frequency division between N and N+1. Here, the number of frequency division refers to a setting value by which the frequency of a clock pulse signal is divided, and is set in a frequency division counter that counts the pulses of the clock pulse signal.
Meanwhile, in one conventional attempt to reduce the circuit size of a frequency division counter and a comparison circuit, a prescaler is used to divide the frequency of a high-speed clock signal to generate a clock source signal for the frequency division counter. However, the use of the prescaler is not practically applicable to the conventional frequency division as shown in the aforementioned Patent Document 1, namely a method for causing an average frequency of two generated clock signals to approximate a frequency having a predetermined cycle. Specifically, if the prescaler is used in the method of the Patent Document 1, the cycle of a clock signal generated based on the cycle of a clock signal output from the prescaler varies. Therefore, although the cycle of the clock signal is supposed to approximate an ideal cycle, a phase difference between the generated clock signal and the ideal clock signal becomes large, resulting in the circuit not operating normally.
Assume here that the circuit is a communication circuit, that a clock signal having a frequency divided by 6.5 is necessary, and that the prescaler obtains the clock source signal for the frequency division counter by dividing a high-speed clock signal by two. In this case, if a method as shown in the Patent Document 1 is used, a 6.5-frequency-division clock signal is generated with use of one 8-frequency-division clock signal and three 6-frequency-division clock signals ((8+6+6+6)/4=6.5). However, since a phase difference between the 8-frequency-division clock signal and the ideal 6.5-frequency-division clock signal is substantially equivalent to 1.5 cycles of the high-speed clock signal, the circuit sometimes fails to operate normally.